EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
EDN

Gate level simulations: verification flow and challenges

Simulations are an important part of the verification cycle in the process of hardware designing. It can be performed at varying degrees of physical abstraction: In many companies RTL simulations is ...
Design-Reuse

Socionext Adopts Defacto Solution for RTL and Gate-level Design Analysis and Building

Grenoble, France, June 1 st, 2015 ---Defacto Technologies S.A. today announced that Socionext Inc., a leading provider of System-on-Chip solutions, has adopted Defacto Technologies’ STAR RTL Design ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Electronic Design

Extending Formal Verification Methodologies Beyond The Gate Level

In recent years, formal verification has become the verification methodology of choice for many designers and verification engineers. It's now in the mainstream marketplace, as it's easy to use, ...
Semiconductor Engineering

Verification As A Flow (Part 2)

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Semiconductor Engineering

Reducing Power At RTL

Power management and reduction at the register transfer level is becoming more problematic as more heterogeneous elements are added into advanced designs and more components are dependent on ...