EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Business Insider

Mentor Graphics Expands Formal Verification's Reach with New Cross-Platform GUI and Apps for Sequential Logic Equivalence Checking and CDC Gate-Level Analysis

WILSONVILLE, Ore., April 20, 2017 /PRNewswire/ -- Mentor, a Siemens business, today announced new formal-based technologies in the Questa Verification Solution that provide RTL designers and ...
EDN

Gate level simulations: verification flow and challenges

Simulations are an important part of the verification cycle in the process of hardware designing. It can be performed at varying degrees of physical abstraction: In many companies RTL simulations is ...
Design-Reuse

Xilinx, Verplex Collaborate to Provide Formal Verification At Various Stages of FPGA Design Flow

SAN JOSE & MILPITAS, Calif.--(BUSINESS WIRE)--Aug. 27, 2001-- Xilinx, Inc. and Verplex(TM) Systems, Inc., today launched one of the first formal verification environments specifically for the design ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...