Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
Semiconductor Engineering

Balancing Leakage Reduction with Correctness Preservation in RTL Code Generation (Univ. of Central Florida)

Mitigating LLM Memorization in RTL Code Generation Against IP Leakage” was published by researchers at University of Central Florida. Abstract “Large Language Models (LLMs) have achieved remarkable ...
EDN

SunaptiCAD VeriLogger Extreme: Verilog 2001 simulator provides faster RTL and gate-level simulations

Reducing simulation debugging time, the compiled-code Verilogger Extreme Verilog 2001 simulator provides fast simulation of RTL and gate-level simulations using SDF (Synopsys Delay Format) timing ...