EDN

Agere to pull Cadence partitioning, sign-off tool into ASIC flow

ALLENTOWN, Pa. — Agere Systems is working with San Jose, California-based Cadence Design Systems Inc. to provide Agere ASIC customers with access to Cadence's “First Encounter” EDA software. This is ...
Nasdaq

Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications

Cadence Innovus Implementation System and Voltus IC Power Integrity Solution enable GUC to achieve first-pass silicon success and meet GHz performance target for multi-billion gate designs Traditional ...
Design-Reuse

Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design

SAN JOSE, Calif. -- Jan 10, 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, today announced significant new advancements to help boost ...
Business Wire

GUC Optimizes Quality of Results and Accelerates Time to Tapeout Using the Cadence Digital Full Flow

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Global Unichip Corporation (GUC) used the Cadence ® digital full flow to accelerate the time to tapeout ...
EDN

Cadence supports structured ASIC design

SANTA CRUZ, Calif. — Cadence Design Systems has announced that its SoC Encounter IC physical design platform is providing “back end” support for structured ASICs from both NEC Electronics and Faraday ...
Nasdaq

Cadence and UMC Certify mmWave Reference Flow on 28HPC+ Process for Advanced RF Designs

Collaboration enables customers to utilize Cadence RF solutions to design 5G, IoT and automotive applications on UMC’s 28nm process technology The certified mmWave reference flow supports the Cadence ...
The Globe and Mail

Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of a node-to-node design migration flow based on the Cadence ® Virtuoso ® Design Platform compatible with all TSMC advanced ...
Electronic Design

Fujitsu ships production volumes of structured ASIC

Cadence Design Systems and Fujitsu Microelectronics America (FMA) have announced that FMA is shipping initial production volumes of a new, complex, structured ASIC using Cadence Encounter IC ...
Business Insider

New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board

Solution integrates the Virtuoso platform with Allegro and Sigrity technologies to streamline overall design process and significantly improve productivity and cycle time SAN JOSE, Calif., May 30, ...