Electronics Weekly

The tortoise and the hare in adder design

One of the curious features of low-power circuits in advanced processes is that the lower-voltage option does not always lead to the best overall design. Very often the hare strategy, in which you run ...
TechRepublic

Design and Implementation of 16-Bit Magnitude Comparator Using Efficient Low Power High Performance Full Adders

In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder. The paper attempts to examine the features of certain adder ...
EDN

Design of Adder

In divide & conquer approach the 16 bit number is divided into individual 8 bits. If we continue to divide we reach the leaf level of the problem. In the leaf level of the D&C Tree is a 1 bit adder, ...
Semiconductor Engineering

Applying a Floating Gate Field Effect Transistor To A Logic-in-Memory Application Circuit Design

A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National ...